A three-dimensional stacked semiconductor memory such as a 3D-NAND flash memory includes a laminated film including different kinds of layers alternately formed multiple times (see, for example, Patent Document 1). In the laminated film, a recess portion (hole (opening) or a trench (groove)) penetrating to a base film may be formed, and a plasma etching process is performed to form such a deep recess portion.
In the plasma process of etching such a multilayer film, if etching processes are respectively performed on different layers constituting the laminated film, the number of etching processes increases as the number of layers increases, so that a throughput decreases. For this reason, the plasma etching process is performed on the laminated film with a processing gas including all gases respectively required to etch the different kinds of layers, so that a recess portion penetrating through the different layers can be formed by performing the plasma etching at one time.
When the laminated film is etched as such, a mask layer in which an opening of forming the recess portion on the laminated film is patterned is formed on the laminated film and the laminated film is plasma-etched with the mask layer as a mask. To be specific, it is known that a deep hole is formed by performing a main etching process of performing a plasma etching process and then performing an over etching process of widening a shape of a lower end (bottom portion) (bottom CD value) of the deep hole.    Patent Document 1: Japanese Patent Laid-open Publication No. 2009-266944